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Wednesday, December 14, 2011

PSpice AD student (2 input xor)


*2 INPUT XOR

VDD 3 0 DC 5
VGA 1 0 PULSE(0 5 5U 1N 1N 20U 40U)
VGB 2 0 PULSE(0 5 10U 1N 1N 20U 40U)
M1 4 1 0 0 NMOD1
.MODEL NMOD1 NMOS(VTO=2 KP=4.5E-5 RD=2 RS=2 RDS=1MEG RB=0 RG=0 CGBO=1PF CGDO=1PF CGSO=1PF)

M2 5 2 4 0 NMOD2
.MODEL NMOD2 NMOS(VTO=2 KP=4.5E-5 RD=2 RS=2 RDS=1MEG RB=0 RG=0 CGBO=1PF CGDO=1PF CGSO=1PF)

M3 5 4 2 0 NMOD3
.MODEL NMOD3 NMOS(VTO=2 KP=4.5E-5 RD=2 RS=2 RDS=1MEG RB=0 RG=0 CGBO=1PF CGDO=1PF CGSO=1PF)

M4 6 5 0 0 NMOD4
.MODEL NMOD4 NMOS(VTO=2 KP=4.5E-5 RD=2 RS=2 RDS=1MEG RB=0 RG=0 CGBO=1PF CGDO=1PF CGSO=1PF)

M5 4 1 3 3 PMOD1
.MODEL PMOD1 PMOS(VTO=-2 KP=4.5E-4 RD=2 RS=2 RDS=1MEG RB=0 RG=0 CGBO=1PF CGDO=1PF CGSO=1PF)

M6 5 2 1 3 PMOD2
.MODEL PMOD2 PMOS(VTO=-2 KP=4.5E-4 RD=2 RS=2 RDS=1MEG RB=0 RG=0 CGBO=1PF CGDO=1PF CGSO=1PF)

M7 5 1 2 3 PMOD3
.MODEL PMOD3 PMOS(VTO=-2 KP=4.5E-4 RD=2 RS=2 RDS=1MEG RB=0 RG=0 CGBO=1PF CGDO=1PF CGSO=1PF)

M8 6 5 3 3 PMOD4
.MODEL PMOD4 PMOS(VTO=-2 KP=4.5E-4 RD=2 RS=2 RDS=1MEG RB=0 RG=0 CGBO=1PF CGDO=1PF CGSO=1PF)

.TRAN 1U 80U
.PROBE
.END

circuit diagram


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