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Saturday, December 3, 2011

Full Adder



Full Adder Data flow(CODE)
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    23:56:56 11/23/2011
-- Design Name:
-- Module Name:    Full_Adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Full_Adder is
    Port ( Ain : in  STD_LOGIC;
           Bin : in  STD_LOGIC;
           Cin : in  STD_LOGIC;
           SUM : out  STD_LOGIC;
           Cout : out  STD_LOGIC);
end Full_Adder;

architecture Behavioral of Full_Adder is

begin
SUM<=Ain xor Bin xor Cin;
Cout<= (((Ain xor Bin) and Cin) or (Ain and Bin));


end Behavioral;
-------------------------------------------------------------------------------------------------------------
Full Adder (TEST BENCH)
----------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   00:07:08 11/24/2011
-- Design Name:   
-- Module Name:   C:/Documents and Settings/MAX/Full_Adder_test.vhd
-- Project Name:  MAX
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Full_Adder
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY Full_Adder_test IS
END Full_Adder_test;

ARCHITECTURE behavior OF Full_Adder_test IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Full_Adder
    PORT(
         Ain : IN  std_logic;
         Bin : IN  std_logic;
         Cin : IN  std_logic;
         SUM : OUT  std_logic;
         Cout : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal Ain : std_logic := '0';
   signal Bin : std_logic := '0';
   signal Cin : std_logic := '0';

  --Outputs
   signal SUM : std_logic;
   signal Cout : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 

   

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: Full_Adder PORT MAP (
          Ain => Ain,
          Bin => Bin,
          Cin => Cin,
          SUM => SUM,
          Cout => Cout
        );

  -- We just have to modify the stimulus and if the system contain no signal then all the signal code should be erased

   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ns;

      Ain<='0';
Bin<='0';
Cin<='1';
wait for 100 ns;
Ain<='0';
Bin<='1';
Cin<='0';
wait for 100 ns;
Ain<='0';
Bin<='1';
Cin<='1';
wait for 100 ns;
Ain<='1';
Bin<='0';
Cin<='0';
wait for 100 ns;
Ain<='1';
Bin<='0';
Cin<='1';
wait for 100 ns;
Ain<='1';
Bin<='1';
Cin<='0';
wait for 100 ns;
Ain<='1';
Bin<='1';
Cin<='1';
wait for 100 ns;
      -- insert stimulus here 

      wait;
   end process;

END;





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