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Saturday, December 3, 2011

VHDL Complete Tutorial

VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language.In the mid-1980’s the U.S. Department of Defense and the IEEE sponsored the development of this hardware description language with the goal to develop very high-speed integrated circuit.It has become now one of industry’s standard languages used to describe digital systems. The other widely used hardware description languages are VHDL and Verilog.
 Although these languages look similar as conventional programming languages, there are some important differences. A hardware description language is inherently parallel, i.e. commands, which correspond to logic gates, are executed (computed) in parallel, as soon as a new input arrives. A HDL program mimics the behavior of a physical, usually digital, system. It also allows incorporation of timing specifications (gate delays) as well as to describe a system as an interconnection of different components.

Basic Structure of a VHDL file
A digital system in VHDL consists of a design entity that can contain other entities that are then considered components of the top-level entity. Each entity is modeled by an entity declaration and an architecture body. One can consider the entity declaration as the interface to the outside world that defines the input and output signals, while the architecture body contains the description of the entity and is composed of interconnected entities, processes and components, all operating concurrently, as schematically shown in Figure 3 below. In a typical design there will be many such entities connected together to perform the desired function.

 A VHDL entity consisting of an interface (entity declaration) and a body (architectural description).

A library can be considered as a place where the compiler stores information about a design project. 

To use any of these one must include the library and use clause:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
            use ieee.std_logic_unsigned.all

Entity Declaration:
The entity declaration defines the NAME of the entity and lists the input and output ports. The general form is as follows,
entity NAME_OF_ENTITY is [ generic generic_declarations);]
     port (signal_names: mode type;
            signal_names: mode type;
            signal_names: mode type);
An entity always starts with the keyword entity, followed by its name and the keyword is. Next are the port declarations using the keyword port. An entity declaration always ends with the keyword end, followed by the name of the entity.

  • The NAME_OF_ENTITY is a user-selected identifier
  • mode: is one of the reserved words to indicate the signal direction:
    in – indicates that the signal is an input.
    out – indicates that the signal is an output of the entity whose value can only be read by other entities that use it.
    inout – the signal can be an input or an output.
  • type: a built-in or user-defined signal type. Examples of types are bit, bit_vector, std_logic,std_logic_vector.

Architecture body:
The architecture body specifies how the circuit operates and how it is implemented. As discussed earlier, an entity or circuit can be specified in a variety of ways, such as behavioral, structural (interconnected components), or a combination of the above.
The architecture body looks as follows,
            architecture architecture_name of NAME_OF_ENTITY is
     -- Declarations
           -- components declarations
           -- signal declarations
           -- constant declarations
           -- function declarations
           -- procedure declarations
           -- type declarations
     -- Statements
     end architecture_name;

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